Design Optimization Based on Diagnosis Techniques

Logic optimization is the step of the VLSI design cycle where the designer performs modifications on the design obtained to satisfy different constraints such as area, power or delay. In this paper we propose a novel ATPGbased optimizationmethodology that borrows from previous design error diagnosis and correction techniques. We also present examples and experiments that indicate that our approach has additional potential when compared to previous ATPG/simulation-based optimization methods. Andreas Veneris Magdy S. Abadir Ibrahim N. Hajj University of Toronto Motorola University of Illinois ECE Department 7700 W. Parmer ECE Department and CSL Toronto, ON M5S 3G4 Austin, TX 78729 Urbana, IL 61801 [email protected] [email protected] [email protected] 1 Logic Design Optimization The design of digital circuits usually starts with a behavioral description (specification) coded in some high level description language. At some point of the design cycle, logic synthesis is carried out to obtain a multilevel implementation (netlist) using cells (gates) from some technology library. As a next step, logic optimization is usually performed, where the objective is to modify the netlist to achieve different constraints such as minimize the area, reduce power consumption, satisfy timing constraints, reduce switching noise or improve the testability of the final circuit. Recently, ATPG/simulation-based optimization techniques [6] [7] [8] [9] [10] [11] [16] have gained increasing popularity. Their main strength, compared to formal Boolean function (i.e. symbolic) [4] based optimization methods, lies in their flexibility since they are memory efficient, they have good failure characteristics and although, theoretically, they can be exponential in time, in practice this is rarely the case. In this research we propose a new approach to ATPG-based design optimization. The proposed approach borrows from our previous efforts on Design Error Diagnosis and Correction (DEDC) and it provides a more “powerful” route to ATPG-based optimization. To illustrate the central points of the proposed research we need to take a closer view on existing ATPG-based optimization techniques and the problem of DEDC. This is the topic of sections 2 and 3, respectively. In section 4 we examine the relationship of these two problems and present our method. Section 5 contains the experimental results and section 6 concludes this paper. 2 Design Optimization Via